1. The Field of the Invention
The present invention relates to non-volatile memory cells. More particularly, the present invention relates to an apparatus and method for providing high-density single transistor memory cells for use in semiconductor devices.
2. The Relevant Technology
It is well known that ferroelectric materials may be used to store information in a non-volatile memory cell. Ferroelectric materials possess two characteristics that make them ideal for such use: a bi-stable polarization (positive or negative) that corresponds to a “1” or a “0” digital logic state, and the ability to retain such states in the absence of electrical power to the memory cell. The polarization effect demonstrated by ferroelectric materials is best understood as a non-zero charge per unit area on the ferroelectric device (such as a capacitor) that exists at zero voltage.
A variety of ferroelectric memory (“FEM”) structures are known in the art, including ferroelectric random access memories (“FRAMs”) that employ two transistor-two capacitor (2T/2C) and one transistor-one capacitor (1T/1C) FEM cells on integrated circuit chips. In such FEM cells, the capacitor is generally made by sandwiching a thin ferroelectric film between two electrically conductive electrodes. Also known in the art is the use of a ferroelectric film to form a field effect transistor (“FET”), where the gate of the FET includes a ferroelectric material. A popular type of such ferroelectric gate-controlled devices is the metal-ferroelectric-metal-oxide-silicon (“MFMOS”) FET, often incorporated in FRAMs. FRAMs having MFMOS FET structures are often desired over the transistor-capacitor configurations because they occupy less area on the semiconductor surface, and because they provide non-destructive readout (“NDRO”) of the FRAM cells. With the ever-present drive for circuit size reduction in integrated circuit chip fabrication, however, attention is directed to creating smaller, more compact FEM cells. A need therefore exists to produce a MFMOS FRAM cell that may be incorporated into a high density memory cell array while, at the same time, preserving FRAM circuit designs.